1. Field of the Invention
The present invention relates to a complementary metal-oxide semiconductor (CMOS) image sensor and a method for fabricating the same, and more particularly, to a CMOS image sensor and a method for fabricating the same in which a dead zone and a dark current are simultaneously reduced.
2. Discussion of the Related Art
Generally, an image sensor is a semiconductor device that converts optical images to electrical signals. The image sensor can be classified as a charge coupled device (CCD) and a CMOS image sensor.
The CCD has drawbacks in its fabricating process because of a complicated driving mode, high power consumption, and multistage photolithographic processes. Also, it is difficult for a control circuit, a signal processing circuit, and an analog-to-digital converter to be integrated in a CCD chip. Thus, the CCD is not suitable for use in slim sized products. However, CMOS image sensors have received attention as the next generation technology for overcoming the drawbacks of CCDs.
The CMOS image sensor employs a switching mode that sequentially detects outputs of unit pixels using MOS transistors by forming the MOS transistors to correspond to the number of the unit pixels on a semiconductor substrate. CMOS technology that uses a control circuit and a signal processing circuit as peripheral circuits is employed.
The CMOS image sensor has advantages in that power consumption is low because of the CMOS technology. Also, a fabricating process is simple because of a relatively small number of photolithographic processing steps. Further, since the CMOS image sensor allows a control circuit, a signal processing circuit and an analog-to-digital converter to be integrated in its chip, it has an advantage in that a slim sized product can be obtained. Therefore, the CMOS image sensor is widely used for various application fields such as digital still cameras and digital video cameras.
A related art CMOS image sensor will be described with reference to FIGS. 1 and 2. FIG. 1 is a layout illustrating a unit pixel of a 4T type CMOS image sensor including four transistors, and FIG. 2 is an equivalent circuit 100 diagram illustrating the unit pixel of the CMOS image sensor shown in FIG. 1.
In the unit pixel of the 4T type CMOS image sensor, as shown in FIGS. 1 and 2, a photodiode (PD) 20 is formed in a wide portion of an active area 10, and gate electrodes 110, 120, 130, and 140 of four transistors, are formed to respectively overlap the other portions of the active area 10. A transfer transistor Tx, a reset transistor Rx, a drive transistor Dx, and a selection transistor Sx are respectively formed by the gate electrodes 110, 120, 130 and 140.
Impurity ions are implanted into the active area 10 of each transistor except portions below the gate electrodes 110, 120, 130 and 140, so that source and drain areas of each transistor are formed. Thus, a power voltage Vdd is applied to the source and drain areas between the reset transistor Rx and the drive transistor Dx, and a power voltage Vss is applied to the source and drain areas at one side of the selection transistor Sx.
The transfer transistor Tx transfers optical charges generated by the photodiode to a floating diffusion (FD) layer. The reset transistor Rx controls and resets the potential of the floating diffusion layer. The drive transistor Dx serves as a source follower. The selection transistor Sx serves as a switching transistor to read a signal of the unit pixel.
A method for fabricating the aforementioned related art CMOS image sensor will be described with reference to FIG. 3A to FIG. 3G. FIG. 3A to FIG. 3G are sectional views taken along line I-I′ of the unit pixel of the CMOS image sensor shown in FIG. 1.
First, as shown in FIG. 3A, a lightly doped P type (P-) epitaxial layer 2 is formed on a P type semiconductor substrate 1 defined by an active area and a device isolation area using a mask. Then, the lightly doped P type epitaxial layer 2 is etched at a predetermined depth by exposing and developing processes using the mask to form a trench. An oxide film is formed on the epitaxial layer 2. The trench is filled with the oxide film by a chemical mechanical polishing (CMP) process so as to form a device isolation film 3 in the device isolation area.
Impurity ions are implanted into the surface of the epitaxial layer 2 to correspond to the active area to form a P type impurity ion area 4. The P type impurity ion area 4 is used to control a threshold voltage in a channel area of the transfer transistor and to pin a surface voltage in the photodiode.
As shown in FIG. 3B, a gate insulating film and a conductive layer are sequentially formed on the entire surface of the substrate and then selectively dry-etched to form a gate insulating film 5 and a gate electrode 6 of each transistor including the transfer transistor.
As shown in FIG. 3C, an insulating film 7 such as an oxide film is formed on the entire surface of the substrate including the gate electrode 6 to recover a damaged corner of the gate insulating film 5 and protect the surface of the epitaxial layer 2 during a later ion implantation process.
As shown in FIG. 3D, a photoresist film is coated on the entire surface and then removed by exposing and developing processes to form a photoresist pattern 8 that exposes the photodiode. The photoresist pattern 8 is formed to partially cover the active area adjacent the device isolation film 3 and to partially expose the gate electrode 6. N type impurity ions are implanted into the epitaxial layer 2 of the exposed photodiode by high energy ion implantation to form a photodiode N type impurity ion area 9.
As shown in FIG. 3E, after the photoresist pattern 8 is removed, a photoresist pattern 10 is formed to expose the photodiode. P type impurity ions are implanted into the surface of the photodiode N type impurity ion area 9 to form a P type impurity ion area 11. The P type impurity ion area 11 has a doping level obtained by adding a doping level of the P type impurity ion area 4 thereto.
Instead of the process shown in FIG. 3E, as shown in FIG. 3F, an insulating film may be deposited on the entire surface and then removed by an anisotropic etching process to form spacers 12 at sidewalls of the gate electrode 6. After the photoresist pattern 10 is formed to expose the photodiode, P type impurity ions may be implanted into the surface of the photodiode N type impurity ion area 9 to form the P type impurity ion area 11.
As shown in FIG. 3G, the photoresist pattern 10 is removed, and N type impurity ions are heavily implanted into the drain area at one side of the gate electrode 6 using a mask to form a heavily doped N type impurity ion area 13.
In the related art CMOS image sensor, the photodiode converts signals of light into electrical signals to generate optical charges. The generated optical charges move to the floating diffusion layer so as to gate the drive transistor Dx if the transfer transistor Tx is turned on. However, as shown in FIG. 3E, if the P type impurity ions are implanted before the spacers are formed, the epitaxial layer below the spacers is pinned. Characteristics of a dark current may be improved but the P type impurity ion doping level increases. As the P type impurity ion doping level increases, a potential barrier of the source area of the transfer transistor increases to reduce transfer efficiency of the optical charges. A problem then occurs in that a dead zone is formed. In the dead zone no signal is generated for a certain time period after light enters the sensor.
Furthermore, as shown in FIG. 3F, if the P type impurity ions are implanted after the spacers are formed at the sidewalls of the gate electrode, transfer efficiency of the optical charges may be improved. However, the surface of the photodiode is damaged during the dry-etching process that forms the spacers. Dark current is thereby increased.